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rej03c0394-0100 rev.0.01 2009.12.08 page 1 of 14 r1lv0808asb ? 5si, 7si 8mb advanced lpsram (1024k word x 8bit) rej03c0394-0100 rev.1.00 2009.12.08 description the r1lv0808asb is a family of low voltage 8-mbit static rams organized as 1,048,576-word s by 8-bit, fabricated by renesas's high-performance 0.15um cmos and tft te chnologies. the r1lv08808asb is suitable for me mory applications where a simple interfacing, battery operating and battery backup are the important design objectives. the r1lv0808asb is packaged in a 44pin thin small outline mount device [11.76mm18.41mm 44-pin plastic tsop (ii)]. it gives the best solution for a co mpaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. features single 2.4-3.6v power supply small stand-by current: 1.2 a (vcc=3.0v, typ.) no clocks, no refresh all inputs and outputs are ttl compatible easy memory expansion by cs1# andcs2 common data i/o three-state outputs: or-tie capability oe# prevents data contention in the i/o bus operation temperature: -40 ~ +85c ordering information type no. power supply access time temperature range package 2.7v to 3.6v 55 ns r1lv0808asb-5si 2.4v to 2.7v 70 ns R1LV0808ASB-7SI 2.4v to 3.6v 70 ns -40 ~ +85c 11.76mm18.41mm 44-pin plastic tsop (ii) (normal-bend type) (44p3f)
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 2 of 14 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1# nc nc dq0 dq1 v cc gnd dq2 dq3 nc nc we# a19 a18 a17 a16 a15 a 5 a6 a7 oe# cs2 a8 nc nc dq7 dq6 gnd vcc dq5 dq4 nc nc a9 a10 a11 a12 a13 a14 44-pin tsop (ii)
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 3 of 14 pin description pin name function vcc power supply vss ground a0 to a19 address input (word mode) dq0 to dq7 data input/output cs1# chip select 1 cs2 chip select 2 we# write enable oe# output enable nc non connection
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 4 of 14 block diagram a 0 cs1# a 1 we# oe# a 19 dq0 dq1 dq7 vcc vss column decoder dq buffer address buffer row decoder sense / write amplifier clock generator memory array 1024k-word x8-bit cs2
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 5 of 14 operation table cs1# cs2 we# oe# dq0~7 operation x l x x high-z stand-by h x x x high-z stand-by l h l x din write l h h l dout read l h h h high-z output disable note 1. h: v ih l:v il x: v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to vss vcc -0.5 to +4.6 v terminal voltage on any pin relative to vss v t -0.5 *1 to vcc+0.3 *2 v power dissipation p t 0.7 w operation temperature topr -40 to +85 c storage temperature range tstg -65 to 150 c storage temperature range under bias tbias -40 to +85 c note 1. -3.0v in case of ac (pulse width 30ns) 2. maximum voltage is +4.6v
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 6 of 14 recommend operating conditions parameter symbol min. typ. ma x. unit test conditions note vcc 2.4 3.0 3.6 v - supply voltage vss 0 0 0 v - 2.0 - vcc+0.2 v vcc=2.4v to 2.7v input high voltage v ih 2.2 - vcc+0.2 v vcc=2.7v to 3.6v -0.2 - 0.4 v vcc=2.4v to 2.7v 1 input low voltage v il -0.2 - 0.6 v vcc=2.7v to 3.6v 1 ambient temperature range ta -40 - +85 c - note 1. -3.0v in case of ac (pulse width 30ns) dc characteristics parameter symbol min. typ. max. unit test conditions input leakage current | i li | - - 1 a vin = vss to vcc output leakage current | i lo | - - 1 a cs1# =v ih or cs2 =v il or oe# =v ih or we# =v il , vi/o =vss to vcc i cc1 - 20 *1 35 ma min. cycle, duty =100%, i i/o = 0ma cs1# =v il , cs2 =v ih , others = v ih /v il average operating current i cc2 - 2 *1 5 ma cycle =1 s, duty =100%, i i/o = 0ma cs1# 0.2v, cs2 v cc -0.2v, v ih v cc -0.2v, v il 0.2v standby current i sb - - 1 ma cs2 =v il - 1.2 *1 4 a ~+25c - 3 *2 6 a ~+40c - - 15 a ~+70c standby current i sb1 - - 20 a ~+85c vin 0v (1) 0v cs2 0.2v or (2) cs1# v cc -0.2v, cs2 v cc -0.2v v oh 2.4 - - v i oh = -1ma vcc 2.7v output high voltage v oh2 2.0 - - v i oh = -0.1ma v ol - - 0.4 v i ol = 2ma vcc 2.7v output low voltage v ol2 - - 0.4 v i ol = 0.1ma note 1.typical parameter indicates the value for the center of distribution at 3.0v(ta= +25c), and not 100% tested. 2.typical parameter indicates the value for the center of distribution at 3.0v(ta =+40c), and not 100% tested.
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 7 of 14 capacitance (ta =25c, f =1mhz) parameter symbol min. typ. max. unit test conditions note input capacitance c in - - 10 pf vin =0v 1 input / output capacitance c i/o - - 10 pf v i/o =0v 1 note 1.typical parameter is sampled and not 100% tested. ac characteristics test conditions (vcc = 2.4v ~ 3.6v, ta = -40 ~ +85c) input pulse levels: vil = 0.4v, vi h = 2.4v (vcc = 2.7v ~ 3.6 v) vil = 0.4v, vih = 2.2v (vcc = 2.4v ~ 2.7 v) input rise and fall times: 5ns input and output timing reference level: 1.4v output load: see figures (including scope and jig) dq 1.4v r l = 500 ohm c l = 30 pf
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 8 of 14 read cycle r1lv0808asb-5si (note 0) R1LV0808ASB-7SI parameter symbol min. max. min. max. unit note read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns t acs1 - 55 - 70 ns chip select access time t acs2 - 55 - 70 ns output enable to output valid t oe - 30 - 35 ns output hold from address change t oh 10 - 10 - ns t clz1 10 - 10 - ns 2,3 chip select to output in low-z t clz2 10 - 10 - ns 2,3 output enable to output in low-z t olz 5 - 5 - ns 2,3 t chz1 0 20 0 25 ns 1,2,3 chip deselect to output in high-z t chz2 0 20 0 25 ns 1,2,3 output disable to output in high-z t ohz 0 20 0 25 ns 1,2,3
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 9 of 14 write cycle r1lv0808asb-5si (note 0) R1LV0808ASB-7SI parameter symbol min. max. min. max. unit note write cycle time t wc 55 - 70 - ns address valid to end of write t aw 50 - 65 - ns chip select to end of write t cw 50 - 65 - ns 5 write pulse width t wp 40 - 55 - ns 4 address setup time t as 0 - 0 - ns 6 write recovery time t wr 0 - 0 - ns 7 data to write time overlap t dw 25 - 35 - ns data hold from write time t dh 0 - 0 - ns output enable from end of write t ow 5 - 5 - ns 2 output disable to output in high-z t ohz 0 20 0 25 ns 1,2 write to output in high-z t whz 0 20 0 25 ns 1,2 note 0. if vcc is 2.4-2.7v, parameter s of R1LV0808ASB-7SI (70ns) are applied. 1. t chz , t ohz , t whz and t bhz are defined as the time at which the out puts achieve the open circuit conditions and are not referred to output voltage levels. 2. typical parameter is sampled and not 100% tested. 3. at any given temperatur e and voltage condition, t hz max is less than t lz min both for given device and from device to device. 4. a write occurs during the overlap of a low cs1#, a high cs2, a low we# . a write begins at the latest tr ansitions among cs1# going low, cs2 going high and we# g oing low. a write ends at the earliest transitions among cs 1# going high, cs2 going low and we# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low or cs2 going hig h to the end of write. 6. t as is measured the address valid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# going high or cs2 going low to the end of write cycle
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 10 of 14 timing waveforms read cycle t aa cs1# a 0~19 t oh t clz1 t acs1 t oe t olz t chz1 oe# we# dq 0~7 v ih v il t ohz high impedance we# = ?h? level t rc valid data cs2 t clz2 t acs2 t chz2
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 11 of 14 write cycle (1) (we# clock) cs1# t oh t cw t ow t wc dq 0~7 t dw t dh valid data t ohz oe# we# t aw t as t wp t wr t whz t olz a 0~19 cs2 t cw
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 12 of 14 write cycle (2) (cs1#, cs2 clock) cs1# a 0~19 t cw t wc t aw t as t wr oe# we# dq 0~7 v ih v il oe# = ?h? level t dw t dh t wp valid data cs2 t cw t wr t as
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 13 of 14 data retention characteristics parameter symbol min. typ. max. unit test conditions *3 v cc for data retention v dr 1.5 - 3.6 v vin 0v (1) 0v cs2 0.2v or (2) cs1# v cc -0.2v, cs2 v cc -0.2v - 1.2 *1 4 a ~+25c - 3 *2 6 a ~+40c - - 15 a ~+70c data retention current i ccdr - - 20 a ~+85c vcc=3.0v, vin 0v (1) 0v cs2 0.2v or (2) cs1# v cc -0.2v, cs2 v cc -0.2v chip select to data retention time t cdr 0 - - ns operation recovery time t r 5 - - ms see retention waveform. note 1.typical parameter indicates the value for the center of distribution at 3.0v(ta= +25c), and not 100% tested. 2.typical parameter indicates the value for the center of distribution at 3.0v(ta =+40c), and not 100% tested. 3.cs2 controls address buffer, we# buffer, cs1# buffer, oe# buffer and din buffer. if cs2 controls data retention mode, vi n levels (address, we#, oe #, dq ) can be in the high impedance state. if cs1# controls data retent ion mode, cs2 must be cs2 v cc -0.2v or 0v cs2 0.2v . the other inputs levels (address, we#, oe#, dq) can be in the high impedance state.
r1lv0808asb ?5si, 7si rej03c0394-0100 rev.0.01 2009.12.08 page 14 of 14 data retention timing waveforms cs1# vcc (1) cs# controlled t cdr t r 2.4v 2.4v 2.0v 2.0v v dr cs1# vcc - 0.2v cs2 vcc (2) cs2 controlled t cdr t r 2.4v 2.4v 0.4v 0.4v v dr 0v cs2 0.2v
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